Conventional chip cooling configurations are shown in FIGS. 1A and 1B. The configurations include one or more semiconductor devices (chips) 1 mounted (by its bottom surface) to a host (package) substrate 2 such as silicon. A large heat sink 3 is mounted to the top of the chip 1, for conducting and dissipating heat into the air via the fins 4 of the heat sink 3. There are several drawbacks to the conventional chip cooling configuration. First, the thickness of the packaged assembly is too large. Second, the surface area of the chip in contact with heat sink is too small, which results in a heat dissipation rate off the chip that is too low. Third, for chips that have active areas that need to be exposed (e.g. image sensors), a tradition heat sink cannot be applied over the active area.
There is a need for a chip cooling configuration that is compatible with chips with exposed active areas, yet adds minimal thickness to the overall size.